# Copyright 2018 Tymoteusz Blazejczyk
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

# Create SystemVerilog with SVUnit

set(depends)
set(defines)
set(includes)

if (STD_OVL_FOUND)
    list(APPEND depends ovl_never_unknown_async)
    list(APPEND defines OVL_ASSERT_ON)
    list(APPEND includes "${STD_OVL_DIR}")
endif()

add_hdl_unit_test(logic_basic_gray2binary_unit_test.sv
    DEPENDS
        ${depends}
        logic_basic_gray2binary
    INCLUDES
        ${includes}
    DEFINES
        ${defines}
)
